Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements

Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear which extend injection can provide an accurate error rate estimation at early stages if be used identify weakest resources in a device. The importance challenges associated with timely, but yet realistic evaluation grow increase complexity both hardware domain, integration different types cores SoC (System-on-Chip), software OS (operating system) required take full advantage available resources. In this paper, we combine analyze data gathered extensive (on final physical CPU hardware) microarchitectural injections xmlns:xlink="http://www.w3.org/1999/xlink">early models). We target standalone Arm Cortex-A5 Cortex-A9 integrated into their bare-metal Linux-based configurations. Combining experimental that covers more than 18 million years device time result 176,000 find presence system DUEs (Detected Unrecoverable Errors) (for reasons) do not significantly impact SDCs (Silent Data Corruptions) solely attributed core. Our analysis demonstrates even considering inclusion, early, pre-silicon microarchitecture-level delivers SDC rates estimations lower bounds for DUE rates.